Requirements

Experience
6–9 years of experience in RTL Design and/or RTL Verification.
Experience contributing to production semiconductor, ASIC, FPGA, or SoC programs.
Demonstrated experience leading technical initiatives and mentoring engineers.
Technical Skills
Excellent knowledge of Verilog and SystemVerilog.
Strong understanding of digital design fundamentals and hardware architecture.
Experience with RTL design, simulation, verification, and debugging.
Familiarity with simulation tools and open-source environments such as Icarus Verilog.
Strong understanding of source control systems including Git and GitHub.
Working knowledge of Python for automation, scripting, and workflow enhancement.
Experience working in Linux command-line environments.
Comfortable using Docker Desktop, Dockerfiles, and containerized development workflows.
AI & Modern Engineering Tools
Comfortable using AI-assisted development tools such as Claude, Cursor, Codex, ChatGPT, GitHub Copilot, or similar platforms.
Ability to effectively leverage AI tools for engineering productivity and problem-solving.
Interest in the application of AI within semiconductor engineering workflows.
Soft Skills
Excellent problem-solving and analytical thinking abilities.
Strong communication and documentation skills.
Ability to work independently with minimal supervision.
High degree of creativity and curiosity when solving complex engineering problems.